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83c748/87C748 80c51 8-bit microcontroller family 2k/64 otp/rom, low pin count preliminary specification supersedes data of 1998 apr 23 ic20 data handbook 1999 apr 15 integrated circuits
philips semiconductors preliminary specification 83c748/87C748 80c51 8-bit microcontroller family 2k/64 otp/rom, low pin count 2 1999 apr 15 description the philips 83c748/87C748 offers the advantages of the 80c51 architecture in a small package and at low cost. the 8xc748 microcontroller is fabricated with philips high-density cmos technology. philips epitaxial substrate minimizes cmos latch-up sensitivity. the 8xc748 contains a 2k 8 rom (83c748) eprom (87C748), a 64 8 ram, 19 i/o lines, a 16-bit auto-reload counter/timer, a four-source, fixed-priority level interrupt structure, and an on-chip oscillator. features ? 80c51 based architecture ? small package sizes 24-pin dip (300 mil askinny dipo) 24-pin shrink small outline package (ssop) 28-pin plcc ? 87C748 available in erasable quartz lid or one-time programmable plastic packages ? wide oscillator frequency range: 3.5 to 16mhz ? low power consumption: normal operation: less than 11ma @ 5v, 12mhz idle mode power-down mode ? 2k 8 rom (83c748) 2k 8 eprom (87C748) ? 64 8 ram ? 16-bit auto reloadable counter/timer ? 10-bit fixed-rate timer ? boolean processor ? cmos and ttl compatible ? well suited for logic replacement, consumer and industrial applications ? led drive outputs pin configurations 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 p3.4/a4 p3.3/a3 p3.2/a2/a10 p3.1/a1/a9 p3.0/a0/a8 p0.2/v pp rst x2 x1 v ss p0.0/asel p1.0/d0 p1.1/d1 p1.2/d2 p1.3/d3 p1.4/d4 p1.5/int0 /d5 p1.6/int1 /d6 p1.7/t0/d7 p3.7/a7 p3.6/a6 p3.5/a5 v cc plastic dual in-line and shrink small outline package plastic leaded chip carrier 4126 5 11 25 19 12 18 p0.1/oepgm pin function 1 p3.4/a4 2 p3.3/a3 3 p3.2/a2/a10 4 p3.1/a1/a9 5 nc* 6 p3.0/a0/a8 7 p0.2/v pp 8 p0.1/oe-pgm 9 p0.0/asel 10 nc* 11 rst 12 x2 13 x1 14 v ss pin function 15 p1.0/d0 16 p1.1/d1 17 p1.2/d2 18 p1.3/d3 19 p1.4/d4 20 p1.5/int0 /d5 21 nc* 22 nc* 23 p1.6/int1 /d6 24 p1.7/t0/d7 25 p3.7/a7 26 p3.6/a6 27 p3.5/a5 28 v cc su00295a * no internal connection ordering information rom eprom 1 temperature range c and package frequency mhz drawing number p83c748ebp n p87C748ebp n otp 0 to +70, plastic dual in-line package 3.5 to 16 sot222-1 p83c748eba a p87C748eba a otp 0 to +70, plastic leaded chip carrier 3.5 to 16 sot261-3 p83c748ebd db p87C748ebd db otp 0 to +70, shrink small outline package 3.5 to 16 sot340-1 note: 1. otp = one time programmable eprom.
philips semiconductors preliminary specification 83c748/87C748 80c51 8-bit microcontroller family 2k/64 otp/rom, low pin count 1999 apr 15 3 block diagram rst x1 x2 v cc v ss ram rom/ eprom acc tmp2 tmp1 alu instruction register pd oscillator psw buffer dptr pcon tcon ie th0 tl0 rth rtl interrupt and timer blocks p1.0p1.7 p3.0p3.7 p0.0p0.2 port 0 drivers ram addr register port 0 latch stack pointer program address register pc incre- menter program counter port 3 drivers port 1 drivers port 3 latch port 1 latch timing and control b register su00296
philips semiconductors preliminary specification 83c748/87C748 80c51 8-bit microcontroller family 2k/64 otp/rom, low pin count 1999 apr 15 4 pin descriptions pin no. mnemonic dip/ ssop lcc type name and function v ss 12 14 i circuit ground potential v cc 24 28 i supply voltage during normal, idle, and power-down operation. p0.0p0.2 86 97 i/o port 0: port 0 is a 3-bit open-drain, bidirectional port. port 0 pins that have 1s written to them float, and in that state can be used as high-impedance inputs. these pins are driven low if the port register bit is written with a 0. the state of the pin can always be read from the port register by the program. p0.0 and p0.1 are open drain bidirectional i/o pins. while these differ from astandard ttlo characteristics, they are close enough for the pins to still be used as general-purpose i/o. port 0 also provides alternate functions for programming the eprom memory as follows: 6 7 n/a v pp (p0.2) programming voltage input. (see note 1). 7 8 i oe/pgm (p0.1) input which specifies verify mode (output enable) or the program mode. oe/pgm = 1 output enabled (verify mode). oe/pgm = 0 program mode. 8 9 i asel (p0.0) input which indicates which bits of the eprom address are applied to port 3. asel = 0 low address byte available on port 3. asel = 1 high address byte available on port 3 (only the three least significant bits are used). p1.0p1.7 1320 1520, 23, 24 i/o port 1: port 1 is an 8-bit bidirectional i/o port with internal pull-ups. port 1 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. as inputs, port 1 pins that are externally pulled low will source current because of the internal pull-ups. (see dc electrical characteristics: i il ). port 1 serves to output the addressed eprom contents in the verify mode and accepts as inputs the value to program into the selected address during the program mode. port 1 also serves the special function features of the 80c51 family as listed below: 18 20 i int0 (p1.5): external interrupt. 19 23 i int1 (p1.6): external interrupt. 20 24 i t0 (p1.7): timer 0 external input. p3.0p3.7 51, 2321 6, 41, 2725 i/o port 3: port 3 is an 8-bit bidirectional i/o port with internal pull-ups. port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. as inputs, port 3 pins that are externally being pulled low will source current because of the pull-ups. (see dc electrical characteristics: i il ). port 3 also functions as the address input for the eprom memory location to be programmed (or verified). the 11-bit address is multiplexed into this port as specified by p0.0/asel. rst 9 11 i reset: a high on this pin for two machine cycles while the oscillator is running, resets the device. an internal diffused resistor to v ss permits a power-on reset using only an external capacitor to v cc . after the device is reset, a 10-bit serial sequence, sent lsb first, applied to reset, places the device in the programming state allowing programming address, data and v pp to be applied for programming or verification purposes. the reset serial sequence must be synchronized with the x1 input. x1 11 13 i crystal 1: input to the inverting oscillator amplifier and input to the internal clock generator circuits. x1 also serves as the clock to strobe in a serial bit stream into reset to place the device in the programming state. x2 10 12 o crystal 2: output from the inverting oscillator amplifier. note: 1. when p0.2 is at or close to 0 volts, it may affect the internal rom operation. it is recommended that p0.2 be tied to v cc via a small pull-up (e.g. 2k ). absolute maximum ratings 1, 2 parameter rating unit storage temperature range 65 to +150 c voltage from v cc to v ss 0.5 to +6.5 v voltage from any pin to v ss (except v pp ) 0.5 to v cc + 0.5 v power dissipation 1.0 w voltage on v pp pin to v ss 0 to +13.0 v maximum i ol per i/o pin 10 ma notes: 1. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any conditions other than those described in the ac and dc electrical characteri stics section of this specification is not implied. 2. this product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima.
philips semiconductors preliminary specification 83c748/87C748 80c51 8-bit microcontroller family 2k/64 otp/rom, low pin count 1999 apr 15 5 dc electrical characteristics t amb = 0 c to +70 c, v cc = 5v 10%, v ss = 0v 1 symbol parameter test conditions limits unit symbol parameter test conditions min max unit v il input low voltage 0.5 0.2v dd 0.1 v v ih input high voltage, except x1, rst 0.2v cc +0.9 v cc +0.5 v v ih1 input high voltage, x1, rst 0.7v cc v cc +0.5 v p0.2 v il1 input low voltage 0.5 0.3v cc v v ih2 input high voltage 0.7v cc v cc +0.5 v v ol output low voltage, ports 1 and 3 i ol = 1.6ma 2 0.45 v v ol1 output low voltage, port 0.2 i ol = 3.2ma 2 0.45 v v oh output high voltage, ports 1 and 3 i oh = 60 m a 2.4 v i oh = 25 m a 0.75v cc v i oh = 10 m a 0.9v cc v port 0.0 and 0.1 drivers v ol2 output low voltage i ol = 3ma 0.4 v driver, receiver combined: (over v cc range) c capacitance 10 pf i il logical 0 input current, ports 1 and 3 v in = 0.45v 50 m a i tl logical 1 to 0 transition current, ports 1 and 3 3 v in = 2v (0 to 70 c) 650 m a i li input leakage current, port 0 0.45 < v in < v cc 10 m a r rst internal pull-down resistor 25 175 k w c io pin capacitance test freq = 1mhz, t amb = 25 c 10 pf i pd power-down current 4 v cc = 2 to v cc max 50 m a v pp v pp program voltage (for 87C748 only) v ss = 0v v cc = 5v 10% t amb = 21 c to 27 c 12.5 13.0 v i pp program current (for 87C748 only) v pp = 13.0v 50 ma i cc supply current (see figure 2) notes: 1. parameters are valid over operating temperature range unless otherwise specified. all voltages are with respect to v ss unless otherwise noted. 2. under steady state (non-transient) conditions, i ol must be externally limited as follows: maximum i ol per port pin: 10ma maximum i ol per 8-bit port: 26ma maximum total i ol for all outputs: 67ma if i ol exceeds the test condition, v ol may exceed the related specification. pins are not guaranteed to sink current greater than the listed test conditions. 3. pins of ports 1 and 3 source a transition current when they are being externally driven from 1 to 0. the transition current r eaches its maximum value when v in is approximately 2v. 4. power-down i cc is measured with all output pins disconnected; port 0 = v cc ; x2, x1 n.c.; rst = v ss . 5. active i cc is measured with all output pins disconnected; x1 driven with t clch , t chcl = 5ns, v il = v ss + 0.5v, v ih = v cc 0.5v; x2 n.c.; rst = port 0 = v cc . i cc will be slightly higher if a crystal oscillator is used. 6. idle i cc is measured with all output pins disconnected; x1 driven with t clch , t chcl = 5ns, v il = v ss + 0.5v, v ih = v cc 0.5v; x2 n.c.; port 0 = v cc ; rst = v ss .
philips semiconductors preliminary specification 83c748/87C748 80c51 8-bit microcontroller family 2k/64 otp/rom, low pin count 1999 apr 15 6 ac electrical characteristics t amb = 0 c to +70 c, v cc = 5v 10%, v ss = 0v 1, 2 16mhz clock variable clock symbol parameter min max min max unit 1/t clcl oscillator frequency: 3.5 12 mhz 3.5 16 mhz external clock (figure 1) t chcx high time 20 20 ns t clcx low time 20 20 ns t clch rise time 20 20 ns t chcl fall time 20 20 ns notes: 1. parameters are valid over operating temperature range unless otherwise specified. all voltages are with respect to v ss unless otherwise noted. 2. load capacitance for ports = 80pf. explanation of the ac symbols each timing symbol has five characters. the first character is always `t' (= time). the other characters, depending on their positions, indicate the name of a signal or the logical status of that signal. the designations are: c clock d input data h logic level high l logic level low q output data t time v valid x no longer a valid logic level z float t chcl t clcl t clch t chcx v cc 0.5 0.45v 0.2 v cc + 0.9 0.2 v cc 0.1 t clcx su00297 figure 1. external clock drive rom code submission when submitting rom code for the 83c748, the following must be specified: 1. 2k byte user rom data address content bit(s) comment 0000h to 07ffh data 7:0 user rom data
philips semiconductors preliminary specification 83c748/87C748 80c51 8-bit microcontroller family 2k/64 otp/rom, low pin count 1999 apr 15 7 4mhz 8mhz 12mhz 16mhz freq max active i cc 5 typ active i cc 5 max idle i cc 6 typ idle i cc 6 i cc (ma) 2 4 6 8 10 12 14 16 18 20 22 su00298 figure 2. i cc vs. freq maximum i cc values taken at v cc max and worst case temperature. typical i cc values taken at v cc = 5.0v and 25 c. notes 5 and 6 refer to dc electrical characteristics. oscillator characteristics x1 and x2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator. to drive the device from an external clock source, x1 should be driven while x2 is left unconnected. there are no requirements on the duty cycle of the external clock signal, because the input to the internal clock circuitry is through a divide-by-two flip-flop. however, minimum and maximum high and low times specified in the data sheet must be observed. reset a reset is accomplished by holding the rst pin high for at least two machine cycles (24 oscillator periods), while the oscillator is running. to insure a good power-up reset, the rst pin must be high long enough to allow the oscillator time to start up (normally a few milliseconds) plus two machine cycles. at power-up, the voltage on v cc and rst must come up at the same time for a proper start-up. idle mode in idle mode, the cpu puts itself to sleep while all of the on-chip peripherals stay active. the instruction to invoke the idle mode is the last instruction executed in the normal operating mode before the idle mode is activated. the cpu contents, the on-chip ram, and all of the special function registers remain intact during this mode. the idle mode can be terminated either by any enabled interrupt (at which time the process is picked up at the interrupt service routine and continued), or by a hardware reset which starts the processor in the same manner as a power-on reset. power-down mode in the power-down mode, the oscillator is stopped and the instruction to invoke power-down is the last instruction executed. only the contents of the on-chip ram are preserved. a hardware reset is the only way to terminate the power-down mode. the control bits for the reduced power modes are in the special function register pcon. table 1. external pin status during idle and power-down modes mode port 0 port 1 port 2 idle data data data power-down data data data
philips semiconductors preliminary specification 83c748/87C748 80c51 8-bit microcontroller family 2k/64 otp/rom, low pin count 1999 apr 15 8 differences between the 8xc748 and the 80c51 memory organization the central processing unit (cpu) manipulates operands in two address spaces as shown in figure 3. the part's internal memory space consists of 2k bytes of program memory, and 64 bytes of data ram overlapped with the 128-byte special function register area. the differences from the 80c51 are in ram size (64 bytes vs. 128 bytes), in external ram access (not available on the 83c748), in internal rom size (2k bytes vs. 4k bytes), and in external program memory expansion (not available on the 83c748). the 128-byte special function register (sfr) space is accessed as on the 80c51 with some of the registers having been changed to reflect changes in the 83c748 peripheral functions. the stack may be located anywhere in internal ram by loading the 8-bit stack pointer (sp). it should be noted that stack depth is limited to 64 bytes, the amount of available ram. a reset loads the stack pointer with 07 (which is pre-incremented on a push instruction). program memory on the 8xc748, program memory is 2048 bytes long and is not externally expandable, so the 80c51 instructions movx, ljmp, and lcall are not implemented. the only fixed locations in program memory are the addresses at which execution is taken up in response to reset and interrupts, which are as follows: program memory event address reset 000 external int0 003 counter/timer 0 00b external int1 013 timer i 01b counter/timer subsystem the 8xc748 has one counter/timer called timer/counter 0. its operation is similar to mode 2 operation on the 80c51, but is extended to 16 bits with 16 bits of autoload. the controls for this counter are centralized in a single register called tcon. timer i is available for use as a fixed 10-bit time-base, or as a watchdog. counter timer special function register the counter/timer has only one mode of operation, so the tmod sfr is not used. there is also only one counter/timer, so there is no need for the tl1 and th1 sfrs found on the 80c51. these have been replaced on the 8xc748 by rtl and rth, the counter/timer reload registers. table 2 shows the special function registers, their locations, and reset values. interrupt subsystem fixed priority the ip register and the 2-level interrupt system of the 80c51 are eliminated. simultaneous interrupt conditions are resolved by a single-level, fixed priority as follows: highest priority: pin int0 counter/timer flag 0 pin int1 lowest priority: timer i special function register interrupt subsystem because the interrupt structure is single level on the 83c748, there is no need for the ip sfr, so it is not used. special function register serial communications the 8xc748 contains many of the special function registers (sfr) that are found on the 80c51. due to the different peripheral features on the 8xc748, there are several additional sfrs. since the uart found on 80c51 has been removed, the uart sfrs scon and sbuf have also been removed. i/o port latches (p0, p1, p3) the port latches function the same as those on the 80c51. since there is no port 2 on the 83c748, the p2 latch is not used. port 0 on the 83c748 has only 3 bits, so only 3 bits of the p0 sfr have a useful function. data pointer (dptr) the data pointer (dptr) consists of a high byte (dph) and a low byte (dpl). in the 80c51 this register allows the access of external data memory using the movx instruction. since the 83c748 does not support movx or external memory accesses, this register is generally used as a 16-bit offset pointer of the accumulator in a movc instruction. dptr may also be manipulated as two independent 8-bit registers. special function registers internal data ram (ffh) 255 (80h) 128 (3fh) 63 (00h) 0 su00299 figure 3. memory map
philips semiconductors preliminary specification 83c748/87C748 80c51 8-bit microcontroller family 2k/64 otp/rom, low pin count 1999 apr 15 9 table 2. 8xc748 special function registers symbol description direct address bit address, symbol, or alternative port function msb lsb reset value acc* accumulator e0h e7 e6 e5 e4 e3 e2 e1 e0 00h b* b register f0h f7 f6 f5 f4 f3 f2 f1 f0 00h dptr: dph dpl data pointer (2 bytes) high byte low byte 83h 82h 00h 00h af ae ad ac ab aa a9 a8 ie*# interrupt enable abh ea eti ex1 et0 ex0 00h 82 81 80 p0*# port 0 80h xxxxx111b 97 96 95 94 93 92 91 90 p1* port 1 90h t0 int1 int0 ffh p3* port 3 b0h b7 b6 b5 b4 b3 b2 b1 b0 ffh pcon# power control 87h pd idl xxxxxx00b d7 d6 d5 d4 d3 d2 d1 d0 psw* program status word d0h cy ac f0 rs1 rs0 ov p 00h sp stack pointer 81h 07h 8f 8e 8d 8c 8b 8a 89 88 tcon*# timer/counter control 88h gate c/t tf tr ie0 it0 ie1 it1 00h tl# timer low byte 8ah 00h th# timer high byte 8ch 00h df de dd dc db da d9 d8 ticon*# timer i control d8h/rd 0 tirun 0000xx00b wr clrti tirun rtl# timer low reload 8bh 00h rth# timer high reload 8dh 00h * sfrs are bit addressable. # sfrs are modified from or added to the 80c51 sfrs. i/o port structure the 8xc748 has two 8-bit ports (ports 1 and 3) and one 3-bit port (port 0). all three ports on the 8xc748 are bidirectional. each consists of a latch (special function register p0, p1, p3), an output driver, and an input buffer. three port 1 pins and two port 0 pins are multifunctional. in addition to being port pins, these pins serve the function of special features as follows: port pin alternate function p1.5 int0 (external interrupt 0 input) p1.6 int1 (external interrupt 1 input) p1.7 t0 (timer 0 external input) ports 1 and 3 are identical in structure to the same ports on the 80c51. the structure of port 0 on the 8xc748 is similar to that of the 80c51 but does not include address/data input and output circuitry. as on the 80c51, ports 1 and 3 are quasi-bidirectional while port 0 is bidirectional with no internal pullups. timer/counter the 8xc748 has two timers: a 16-bit timer/counter and a 10-bit fixed-rate timer. the 16-bit timer/counter's operation is similar to mode 2 operation on the 80c51, but is extended to 16 bits. the timer/counter is clocked by either 1/12 the oscillator frequency or by transitions on the t0 pin. the c/t pin in special function register tcon selects between these two modes. when the tcon tr bit is set, the timer/counter is enabled. register pair th and tl are incremented by the clock source. when the register pair overflows, the register pair is reloaded with the values in registers rth and rtl. the value in the reload registers is left unchanged. see the 83c748 counter/timer block diagram in figure 4. the tf bit in special function register tcon is set on counter overflow and, if the interrupt is enabled, will generate an interrupt.
philips semiconductors preliminary specification 83c748/87C748 80c51 8-bit microcontroller family 2k/64 otp/rom, low pin count 1999 apr 15 10 tcon register msb lsb gate c/t tf tr ie0 it0 ie1 it1 gate 1 timer/counter is enabled only when int0 pin is high, and tr is 1. 0 timer/counter is enabled when tr is 1. c/t 1 counter/timer operation from t0 pin. 0 timer operation from internal clock. tf 1 set on overflow of th. 0 cleared when processor vectors to interrupt routine and by reset. tr 1 timer/counter enabled. 0 timer/counter disabled. ie0 1 edge detected in int0 . it0 1 int0 is edge triggered. 0 int0 is level sensitive. ie1 1 edge detected on int1 . it1 1 int1 is edge triggered. 0 int1 is level sensitive. these flags are functionally identical to the corresponding 80c51 flags, except that there is only one timer on the 83c748 and the flags are therefore combined into one register. note that the positions of the ie0/it0 and ie1/it1 bits are transposed from the positions used in the standard 80c51 tcon register. timer i implementation timer i is clocked once per machine cycle, which is the oscillator frequency divided by 12. the timer operation is enabled by setting the tirun bit (bit 4) in the i2cfg register. writing a 0 into the tirun bit will stop and clear the timer. the timer is 10 bits wide, and when it reaches the terminal count of 1024, it carries out and sets the timer i interrupt flag. an interrupt will occur if the timer i interrupt is enabled by bit eti (bit 4) of the interrupt enable (ie) register, and global interrupts are enabled by bit ea (bit 7) of the same ie register. the vector address for the timer i interrupt is 1bhex, and the interrupt service routine must start at this address. as with all 8051 family microcontrollers, only the program counter is pushed onto the stack upon interrupt (other registers that are used both by the interrupt service routine and elsewhere must be explicitly saved). the timer i interrupt flag is cleared by setting the ckrti bit (bit 5 of the i1cfg register. for more information, see application note an427. interrupts the interrupt structure is a four-source, one-level interrupt system. interrupt sources common to the 80c51 are the external interrupts (int0 , int1 ) and the timer/counter interrupt (et0). timer i interrupt (eti) is the other interrupt source. the interrupt sources are listed below in their order of polling sequence priority. upon interrupt or reset the program counter is loaded with specific values for the appropriate interrupt service routine in program memory. these values are: program memory event address priority reset 000 highest int0 003 counter/timer 0 00b int1 013 timer i 01b lowest the interrupt enable register (ie) is used to individually enable or disable the four sources. bit ea in the interrupt enable register can be used to globally enable or disable all interrupt sources. the interrupt enable register is described below. all other interrupt details are based on the 80c51 interrupt architecture. interrupt enable register ea x x e eti ex1 et0 ex0 symbol position function ea ie.7 disables all interrupts. if ea = 0, no interrupt will be acknowledged. if ea = 1, each interrupt source is individually enabled or disabled by setting or clearing its enable bit ie.6 reserved ie.5 reserved ie.4 reserved eti ie.3 enables or disables the timer i overflow interrupt. if et1 = 0, the timer i interrupt is disabled. ex1 ie.2 enables or disables external interrupt 1. if ex1 = 0, external interrupt 1 is disabled. et0 ie.1 enables or disables the timer 0 overflow interrupt. if et0 = 0, thetimer 0 interrupt is disabled. ex0 ie.0 enables or disables external interrupt 0. if ex0 = 0, external interrupt 0 is disabled. osc 12 tl th tf rtl rth t0 pin tr gate int0 pin int. c/t = 0 c/t = 1 reload su00300 figure 4. 83c748 counter/timer block diagram
philips semiconductors preliminary specification 83c748/87C748 80c51 8-bit microcontroller family 2k/64 otp/rom, low pin count 1999 apr 15 11 87C748 programming considerations eprom characteristics the 87C748 is programmed by using a modified quick-pulse programming algorithm similar to that used for devices such as the 87c451 and 87c51. it differs from these devices in that a serial data stream is used to place the 87C748 in the programming mode. figure 5 shows a block diagram of the programming configuration for the 87C748. port pin p0.2 is used as the programming voltage supply input (v pp signal). port pin p0.1 is used as the program (pgm/) signal. this pin is used for the 25 programming pulses. port 3 is used as the address input for the byte to be programmed and accepts both the high and low components of the eleven bit address. multiplexing of these address components is performed using the asel input. the user should drive the asel input high and then drive port 3 with the high order bits of the address. asel should remain high for at least 13 clock cycles. asel may then be driven low which latches the high order bits of the address internally. the high address should remain on port 3 for at least two clock cycles after asel is driven low. port 3 may then be driven with the low byte of the address. the low address will be internally stable 13 clock cycles later. the address will remain stable provided that the low byte placed on port 3 is held stable and asel is kept low. note: asel needs to be pulsed high only to change the high byte of the address. port 1 is used as a bidirectional data bus during programming and verify operations. during programming mode, it accepts the byte to be programmed. during verify mode, it provides the contents of the eprom location specified by the address which has been supplied to port 3. the xtal1 pin is the oscillator input and receives the master system clock. this clock should be between 1.2 and 6mhz. the reset pin is used to accept the serial data stream that places the 87C748 into various programming modes. this pattern consists of a 10-bit code with the lsb sent first. each bit is synchronized to the clock input, x1. programming operation figures 6 and 7 show the timing diagrams for the program/verify cycle. reset should initially be held high for at least two machine cycles. p0.1 (pgm/) and p0.2 (v pp ) will be at v oh as a result of the reset operation. at this point, these pins function as normal quasi-bidirectional i/o ports and the programming equipment may pull these lines low. however, prior to sending the 10-bit code on the reset pin, the programming equipment should drive these pins high (v ih ). the reset pin may now be used as the serial data input for the data stream which places the 87C748 in the programming mode. data bits are sampled during the clock high time and thus should only change during the time that the clock is low. following transmission of the last data bit, the reset pin should be held low. next the address information for the location to be programmed is placed on port 3 and asel is used to perform the address multiplexing, as previously described. at this time, port 1 functions as an output. a high voltage v pp level is then applied to the v pp input (p0.2). (this sets port 1 as an input port). the data to be programmed into the eprom array is then placed on port 1. this is followed by a series of programming pulses applied to the pgm/ pin (p0.1). these pulses are created by driving p0.1 low and then high. this pulse is repeated until a total of 25 programming pulses have occurred. at the conclusion of the last pulse, the pgm/ signal should remain high. the v pp signal may now be driven to the v oh level, placing the 87C748 in the verify mode. (port 1 is now used as an output port). after four machine cycles (48 clock periods), the contents of the addressed location in the eprom array will appear on port 1. the next programming cycle may now be initiated by placing the address information at the inputs of the multiplexed buffers, driving the v pp pin to the v pp voltage level, providing the byte to be programmed to port1 and issuing the 26 programming pulses on the pgm/ pin, bringing v pp back down to the v c level and verifying the byte. programming modes the 87C748 has four programming features incorporated within its eprom array. these include the user eprom for storage of the application's code, a 16-byte encryption key array and two security bits. programming and verification of these four elements are selected by a combination of the serial data stream applied to the reset pin and the voltage levels applied to port pins p0.1 and p0.2. the various combinations are shown in table 3. table 3. implementing program/verify modes operation serial code p0.1 (pgm/) p0.2 (v pp ) program user eprom 296h * v pp verify user eprom 296h v ih v ih program key eprom 292h * v pp verify key eprom 292h v ih v ih program security bit 1 29ah * v pp program security bit 2 298h * v pp verify security bits 29ah v ih v ih note: * pulsed from v ih to v il and returned to v ih . encryption key table the 87C748 includes a 16-byte eprom array that is programmable by the end user. the contents of this array can then be used to encrypt the program memory contents during a program memory verify operation. when a program memory verify operation is performed, the contents of the program memory location is xnor'ed with one of the bytes in the 16-byte encryption table. the resulting data pattern is then provided to port 1 as the verify data. the encryption mechanism can be disable, in essence, by leaving the bytes in the encryption table in their erased state (ffh) since the xnor product of a bit with a logical one will result in the original bit. the encryption bytes are mapped with the code memory in 16-byte groups. the first byte in code memory will be encrypted with the first byte in the encryption table; the second byte in code memory will be encrypted with the second byte in the encryption table and so forth up to and including the 16the byte. the encryption repeats in 16-byte groups; the 17th byte in the code memory will be encrypted with the first byte in the encryption table, and so forth.
philips semiconductors preliminary specification 83c748/87C748 80c51 8-bit microcontroller family 2k/64 otp/rom, low pin count 1999 apr 15 12 security bits two security bits, security bit 1 and security bit 2, are provided to limit access to the user eprom and encryption key arrays. security bit 1 is the program inhibit bit, and once programmed performs the following functions: 1. additional programming of the user eprom is inhibited. 2. additional programming of the encryption key is inhibited. 3. verification of the encryption key is inhibited. 4. verification of the user eprom and the security bit levels may still be performed. (if the encryption key array is being used, this security bit should be programmed by the user to prevent unauthorized parties from reprogramming the encryption key to all logical zero bits. such programming would provide data during a verify cycle that is the logical complement of the user eprom contents). security bit 2, the verify inhibit bit, prevents verification of both the user eprom array and the encryption key arrays. the security bit levels may still be verified. programming and verifying security bits security bits are programmed employing the same techniques used to program the user eprom and key arrays using serial data streams and logic levels on port pins indicated in table 3. when programming either security bit, it is not necessary to provide address or data information to the 87C748 on ports 1 and 3. verification occurs in a similar manner using the reset serial stream shown in table 3. port 3 is not required to be driven and the results of the verify operation will appear on ports 1.6 and 1.7. ports 1.7 contains the security bit 1 data and is a logical one if programmed and a logical zero if not programmed. likewise, p1.6 contains the security bit 2 data and is a logical one if programmed and a logical zero if not programmed. eprom programming and verification t amb = 21 c to +27 c, v cc = 5v 10%, v ss = 0v symbol parameter min max unit 1/t clcl oscillator/clock frequency 1.2 6 mhz t avgl 1 address setup to p0.1 (prog) low 10 m s + 24t clcl t ghax address hold after p0.1 (prog) high 48t clcl t dvgl data setup to p0.1 (prog) low 38t clcl t ghdx data hold after p0.1 (prog) high 36t clcl t shgl v pp setup to p0.1 (prog) low 10 m s t ghsl v pp hold after p0.1 (prog) 10 m s t glgh p0.1 (prog) width 90 110 m s t avqv 2 v pp low (v cc ) to data valid 48t clcl t ghgl p0.1 (prog) high to p0.1 (prog) low 10 m s t masel asel high time 13t clcl t hahld address hold time 2t clcl t haset address setup to asel 13t clcl t adsta low address to valid data 48t clcl notes: 1. address should be valid at least 24t clcl before the rising edge of p0.2 (v pp ). 2. for a pure verify mode, i.e., no program mode in between, t avqv is 14t clcl maximum.
philips semiconductors preliminary specification 83c748/87C748 80c51 8-bit microcontroller family 2k/64 otp/rom, low pin count 1999 apr 15 13 a0a10 address strobe programming pulses v pp /v ih voltage source clk source reset control logic 87C748 p3.0p3.7 p0.0/asel p0.1 p0.2 xtal1 reset v cc v ss p1.0p1.7 +5v data bus su00301 figure 5. programming configuration min 2 machine cycles ten bit serial code bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 undefined undefined xtal1 reset p0.2 p0.1 su00302 figure 6. entry into program/verify modes 5v 12.75v 5v 25 pulses t shgl t ghsl t glgh t ghgl 98 m s min 10 m s min t masel t haset t adsta t dvgl t ghdx t avqv verify mode program mode verify mode p0.2 (v pp ) p0.1 (pgm ) p0.0 (asel) port 3 port 1 invalid data valid data data to be programmed invalid data valid data high address low address t hahld t avgl su00303 figure 7. program/verify cycle
philips semiconductors preliminary specification 83c748/87C748 80c51 8-bit microcontroller family, 2k/64 otp/rom, low pin count 1999 apr 15 14 dip24: plastic dual in-line package; 24 leads (300 mil) sot222-1
philips semiconductors preliminary specification 83c748/87C748 80c51 8-bit microcontroller family, 2k/64 otp/rom, low pin count 1999 apr 15 15 plcc28: plastic leaded chip carrer; 28 leads; pedestal sot261-3
philips semiconductors preliminary specification 83c748/87C748 80c51 8-bit microcontroller family, 2k/64 otp/rom, low pin count 1999 apr 15 16 ssop24: plastic shrink small outline package; 24 leads; body width 5.3 mm sot340-1
philips semiconductors preliminary specification 83c748/87C748 80c51 8-bit microcontroller family, 2k/64 otp/rom, low pin count 1999 apr 15 17 notes
philips semiconductors preliminary specification 83c748/87C748 80c51 8-bit microcontroller family, 2k/64 otp/rom, low pin count 1999 apr 15 18 definitions short-form specification e the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition e limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the dev ice at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limi ting values for extended periods may affect device reliability. application information e applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. disclaimers life support e these products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use i n such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes e philips semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. philips semiconductors ass umes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or m ask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right in fringement, unless otherwise specified. philips semiconductors 811 east arques avenue p.o. box 3409 sunnyvale, california 940883409 telephone 800-234-7381 ? copyright philips electronics north america corporation 1999 all rights reserved. printed in u.s.a. date of release: 04-99 document order number: 9397 750 05736
data sheet status objective specification preliminary specification product specification product status development qualification production definition [1] this data sheet contains the design target or goal specifications for product development. specification may change in any manner without notice. this data sheet contains preliminary data, and supplementary data will be published at a later date. philips semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. this data sheet contains final specifications. philips semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. data sheet status [1] please consult the most recently issued datasheet before initiating or completing a design.

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